RWM6050 Pinlist (80RWM6050B) Revision History ----------------- May 16, 2018 - Updated the following signal names to support the Revision B device: A3-A7, B3, B4, B6, B18, C3-C12, C14-C18, D5-D13, D15, D16, D18, E4-E6, E8, E18, E19, F4-F7, F9, F18, G4, G5, G18, G19, H4, H5, H18, H19, J4, J5, J18, J19, K4, K5, K19, L4, L5, M5, Y3-Y7, Y16-Y20, AA7, AA8, AA15, AA16 June 19, 2017 - Corrected signal names: T3, T4, T19, T20 March 14, 2017 - Initial release DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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Signal Ball ------ ------ A1 VSSIO A2 SPI_CSN A3 DNC A4 A4 A5 A5 A6 DNC A7 DNC A8 PCIE_CLKP A9 PCIE_TX0_N A10 PCIE_RX0_N A11 PCIE_RX0_P A12 PCIE_TX1_N A13 PCIE_RX1_N A14 PCIE_PERSTN A15 VSS A16 SYSOSC_XO A17 SYSOSC_XI A18 RESET_N A19 PWM_0 A20 I2C_SCL A21 I2C_SDA A22 VSSIO B1 SPI_SCLK B2 SPI_MISO B3 A2 B4 A3 B5 VSS B6 A6 B7 VSS B8 PCIE_CLKN B9 VSS B10 PCIE_TX0_P B11 VSS B12 PCIE_TX1_P B13 VSS B14 PCIE_RX1_P B15 PCIE_WAKEN B16 REFCLK_TSYNC0 B17 REFCLK_TSYNC1 B18 VSSIO B19 PWM_1 B20 JTAG_TDO B21 JTAG_TCK B22 RESET_OUT C1 SPI_MOSI C2 GPIO_0 C3 A1 C4 VSSIO C5 VSSIO C6 VSSIO C7 VSSIO C8 VSSIO C9 VSSIO C10 VSSIO C11 VSSIO C12 VSSIO C13 PCIE_CLKREQN C14 VSSIO C15 VSSIO C16 VSSIO C17 VSSIO C18 VSSIO C19 VSSIO C20 JTAG_TDI C21 JTAG_TMS C22 MODE0 D1 GPIO_1 D2 GPIO_2 D3 VDDIO D4 VSSIO D5 VSSIO D6 VSSIO D7 VSSIO D8 VSSIO D9 VSSIO D10 VSSIO D11 VSSIO D12 VSSIO D13 VSSIO D14 PLL1_VDDH D15 VSSIO D16 VSSIO D17 PLL0_VDDH D18 VSSIO D19 VDDIO D20 JTAG_SELECT D21 JTAG_TRSTN D22 MODE1 E1 GPIO_3 E2 GPIO_4 E3 GPIO_5 E4 VSS E5 VSSIO E6 A7 E7 VSS E8 AUX_VP2 E9 VSS E10 PCIE_VPH E11 VSS E12 PCIE_RBIAS E13 VSS E14 PLL1_VDDA E15 PLL1_VSSA E16 PLL0_VSSA E17 PLL0_VDDA E18 RCI0_CSN7_S E19 VSSIO E20 DEBUG_TCK E21 FSPI_CLK E22 FSPI_CSN F1 GPIO_6 F2 GPIO_7 F3 GPIO_8 F4 VSSIO F5 VSSIO F6 VSSIO F7 AUX_VPH F8 VSS F9 AUX_VP1 F10 VSS F11 PCIE_VPTX F12 VSS F13 PCIE_VP F14 PLL1_DVDD F15 PLL1_DVSS F16 PLL0_DVSS F17 PLL0_DVDD F18 RCI0_CSN6_S F19 VDDIO F20 VSSIO F21 FSPI_D0 F22 FSPI_D1 G1 GPIO_9 G2 GPIO_10 G3 VSSIO G4 VSSIO G5 VSSIO G6 TSENSE_AVDDH G7 TSENSE_AVSS G8 VDD G9 VSS G10 VDD G11 VSS G12 VDD G13 VSS G14 VDDIO G15 VSSIO G16 VDD G17 VSSIO G18 RCI0_CSN5_S G19 RCI0_CSN4_S G20 DEBUG_TDO G21 FSPI_D2_WPN G22 FSPI_D3_HN H1 GPIO_11 H2 GPIO_12 H3 VDDIO H4 VSSIO H5 VSSIO H6 VSSIO H7 VDD H8 VSS H9 VDD H10 VSS H11 VDD H12 VSS H13 VDD H14 VSS H15 VDD H16 VSS H17 VDDIO H18 RCI0_CSN3_S H19 VSSIO H20 DEBUG_TDI H21 UART_RTS H22 UART_RX J1 GPIO_13 J2 GPIO_14 J3 GPIO_15 J4 RCI1_CSN6_S J5 RCI1_CSN7_S J6 VDDIO J7 VSS J8 VDD J9 VSS J10 VDD J11 VSS J12 VDD J13 VSS J14 VDD J15 VSS J16 VDD J17 VSS J18 RCI0_CSN2_S J19 RCI0_MISO7_S J20 DEBUG_TMS J21 UART_CTS J22 UART_TX K1 RCI1_GPIO0 K2 RCI1_GPIO1 K3 RCI1_GPIO2 K4 RCI1_CNS4_S K5 RCI1_CSN5_S K6 VSS K7 VDD K8 VSS K9 VDD K10 VSS K11 VDD K12 VSS K13 VDD K14 VSS K15 VDD K16 VSS K17 VDD K18 VSSIO K19 VSSIO K20 DEBUG_TRSTN K21 RCI0_GPIO1 K22 RCI0_GPIO0 L1 RCI1_GPIO3 L2 RCI1_GPIO4 L3 RCI1_GPIO5 L4 RCI1_CSN2_S L5 RCI1_CSN3_S L6 VDDIO L7 VSS L8 VDD L9 VSS L10 VDD L11 VSS L12 VDD L13 VSS L14 VDD L15 VSS L16 VDD L17 VSS L18 VDDIO L19 RCI0_GPIO5 L20 RCI0_GPIO4 L21 RCI0_GPIO3 L22 RCI0_GPIO2 M1 RCI1_CSN0_N M2 RCI1_CSN0_P M3 LVDS_VDDIO M4 VSSIO M5 RCI_1_MISO_7 M6 VSS M7 VDD M8 VSS M9 VDD M10 VSS M11 VDD M12 VSS M13 VDD M14 VSS M15 VDD M16 VSS M17 VDD M18 VSS M19 LVDS_VDDIO M20 VSSIO M21 RCI0_CSN0_P M22 RCI0_CSN0_N N1 RCI1_SCLK_N N2 RCI1_SCLK_P N3 RCI1_GPIO6 N4 RCI1_GPIO7 N5 RCI1_GPIO8 N6 VDDIO N7 VSS N8 VDD N9 VSS N10 VDD N11 VSS N12 VDD N13 VSS N14 VDD N15 VSS N16 VDD N17 VSS N18 RCI0_GPIO8 N19 RCI0_GPIO7 N20 RCI0_GPIO6 N21 RCI0_SCLK_P N22 RCI0_SCLK_N P1 RCI1_MOSI0_N P2 RCI1_MOSI0_P P3 VSSIO P4 LVDS_VDDIO P5 RCI1_GPIO9 P6 VSSIO P7 VDD P8 VSS P9 VDD P10 VSS P11 VDD P12 VSS P13 VDD P14 VSS P15 VDD P16 VSS P17 VDD P18 RCI0_GPIO9 P19 LVDS_VDDIO P20 VSSIO P21 RCI0_MOSI0_P P22 RCI0_MOSI0_N R1 RCI1_MOSI1_N R2 RCI1_MOSI1_P R3 RCI1_REF R4 RCI1_SCLK_S R5 RCI1_CSN0_S R6 VDD R7 VSS R8 VDD R9 VSS R10 VDD R11 VSS R12 VDD R13 VSS R14 VDD R15 VSS R16 VDD R17 VSS R18 RCI0_CSN0_S R19 RCI0_SCLK_S R20 RCI0_REF R21 RCI0_MOSI1_P R22 RCI0_MOSI1_N T1 RCI1_MOSI2_N T2 RCI1_MOSI2_P T3 RCI1_MISO0_S T4 RCI1_MISO1_S T5 RCI1_VDDIO T6 MSFE1_AVSS T7 MSFE1_PLL_AVDD T8 MSFE1_AVSS T9 MSFE1_OSC_AVDDH T10 MSFE1_AVSS T11 MSFE1_AVDD T12 MSFE0_AVDD T13 MSFE0_AVSS T14 MSFE0_OSC_AVDDH T15 MSFE0_AVSS T16 MSFE0_PLL_AVDD T17 MSFE0_AVSS T18 VSSIO T19 RCI0_MISO1_S T20 RCI0_MISO0_S T21 RCI0_MOSI2_P T22 RCI0_MOSI2_N U1 RCI1_MOSI3_N U2 RCI1_MOSI3_P U3 RCI1_MOSI0_S U4 RCI1_MOSI1_S U5 VSSIO U6 MSFE1_AVDDH U7 MSFE1_AVSS U8 MSFE1_PLL_AVDDH U9 MSFE1_AVSS U10 MSFE1_AVDD U11 MSFE1_AVSS U12 MSFE0_AVSS U13 MSFE0_AVDD U14 MSFE0_AVSS U15 MSFE0_PLL_AVDDH U16 MSFE0_AVSS U17 MSFE0_AVDDH U18 RCI0_VDDIO U19 RCI0_MOSI1_S U20 RCI0_MOSI0_S U21 RCI0_MOSI3_P U22 RCI0_MOSI3_N V1 RCI1_CSN1_N V2 RCI1_CSN1_P V3 RCI1_MOSI2_S V4 RCI1_MOSI3_S V5 RCI1_CSN1_S V6 MSFE1_AVSS V7 MSFE1_AVDDH V8 MSFE1_AVSS V9 MSFE1_AVDD V10 MSFE1_AVSS V11 MSFE1_AVSS V12 MSFE0_AVSS V13 MSFE0_AVSS V14 MSFE0_AVDD V15 MSFE0_AVSS V16 MSFE0_AVDDH V17 MSFE0_AVSS V18 RCI0_CSN1_S V19 RCI0_MOSI3_S V20 RCI0_MOSI2_S V21 RCI0_CSN1_P V22 RCI0_CSN1_N W1 VSSIO W2 LVDS_VDDIO W3 VSSIO W4 VDDIO W5 MSFE1_AVSS W6 MSFE1_AVDDH W7 MSFE1_AVSS W8 MSFE1_AVDDH W9 MSFE1_AVSS W10 MSFE1_AVSS W11 MSFE1_AVSS W12 MSFE0_AVSS W13 MSFE0_AVSS W14 MSFE0_AVSS W15 MSFE0_AVDDH W16 MSFE0_AVSS W17 MSFE0_AVDDH W18 MSFE0_AVSS W19 VDDIO W20 VSSIO W21 LVDS_VDDIO W22 VSSIO Y1 MSFE1_ADC_IN Y2 MSFE1_AVSS Y3 RCI1_MISO6_S Y4 RCI1_MISO5_S Y5 RCI1_MISO4_S Y6 RCI1_MISO3_S Y7 RCI1_MISO2_S Y8 MSFE1_AVSS Y9 MSFE1_AVSS Y10 MSFE1_AVSS Y11 MSFE1_AVSS Y12 MSFE0_AVSS Y13 MSFE0_AVSS Y14 MSFE0_AVSS Y15 MSFE0_AVSS Y16 RCI0_MISO2_S Y17 RCI0_MISO3_S Y18 RCI0_MISO4_S Y19 RCI0_MISO5_S Y20 RCI0_MISO6_S Y21 MSFE0_AVSS Y22 MSFE0_ADC_IN AA1 MSFE1_ADC_IP AA2 MSFE1_ADC_VCM AA3 MSFE1_AVSS AA4 MSFE1_CLKOUT AA5 MSFE1_AVSS AA6 MSFE1_AVSS AA7 DNC AA8 DNC AA9 MSFE1_AVSS AA10 MSFE1_AVSS AA11 MSFE1_AVSS AA12 MSFE0_AVSS AA13 MSFE0_AVSS AA14 MSFE0_AVSS AA15 DNC AA16 DNC AA17 MSFE0_AVSS AA18 MSFE0_AVSS AA19 MSFE0_CLKOUT AA20 MSFE0_AVSS AA21 MSFE0_ADC_VCM AA22 MSFE0_ADC_IP AB1 MSFE1_AVSS AB2 MSFE1_ADC_QN AB3 MSFE1_ADC_QP AB4 MSFE1_REFCLKN AB5 MSFE1_REFCLKP AB6 MSFE1_XO AB7 MSFE1_XI AB8 MSFE1_DAC_QN AB9 MSFE1_DAC_QP AB10 MSFE1_DAC_IN AB11 MSFE1_DAC_IP AB12 MSFE0_DAC_IP AB13 MSFE0_DAC_IN AB14 MSFE0_DAC_QP AB15 MSFE0_DAC_QN AB16 MSFE0_XI AB17 MSFE0_XO AB18 MSFE0_REFCLKP AB19 MSFE0_REFCLKN AB20 MSFE0_ADC_QP AB21 MSFE0_ADC_QN AB22 MSFE0_AVSS