RWM6051 Pinlist (80RWM6051B) Revision History ----------------- May 7, 2019 - Initial release DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved. Signal Ball ------ ------ A1 VSSIO A2 SPI_CSN A3 DNC A4 A4 A5 A5 A6 DNC A7 DNC A8 PCIE_CLKP A9 PCIE_TX0_N A10 PCIE_RX0_N A11 PCIE_RX0_P A12 PCIE_TX1_N A13 PCIE_RX1_N A14 PCIE_PERSTN A15 VSS A16 SYSOSC_XO A17 SYSOSC_XI A18 RESET_N A19 PWM_0 A20 I2C_SCL A21 I2C_SDA A22 VSSIO B1 SPI_SCLK B2 SPI_MISO B3 A2 B4 A3 B5 VSS B6 A6 B7 VSS B8 PCIE_CLKN B9 VSS B10 PCIE_TX0_P B11 VSS B12 PCIE_TX1_P B13 VSS B14 PCIE_RX1_P B15 PCIE_WAKEN B16 REFCLK_TSYNC0 B17 REFCLK_TSYNC1 B18 VSSIO B19 PWM_1 B20 JTAG_TDO B21 JTAG_TCK B22 RESET_OUT C1 SPI_MOSI C2 GPIO_0 C3 A1 C4 VSSIO C5 VSSIO C6 VSSIO C7 VSSIO C8 VSSIO C9 VSSIO C10 VSSIO C11 VSSIO C12 VSSIO C13 PCIE_CLKREQN C14 VSSIO C15 VSSIO C16 VSSIO C17 VSSIO C18 VSSIO C19 VSSIO C20 JTAG_TDI C21 JTAG_TMS C22 MODE0 D1 GPIO_1 D2 GPIO_2 D3 VDDIO D4 VSSIO D5 VSSIO D6 VSSIO D7 VSSIO D8 VSSIO D9 VSSIO D10 VSSIO D11 VSSIO D12 VSSIO D13 VSSIO D14 PLL_VDDH D15 VSSIO D16 VSSIO D17 PLL_VDDH D18 VSSIO D19 VDDIO D20 JTAG_SELECT D21 JTAG_TRSTN D22 MODE1 E1 GPIO_3 E2 GPIO_4 E3 GPIO_5 E4 VSS E5 VSSIO E6 A7 E7 VSS E8 DNC E9 VSS E10 PCIE_VPH E11 VSS E12 PCIE_RBIAS E13 VSS E14 PLL_VDDA E15 PLL_VSSA E16 PLL_VSSA E17 PLL_VDDA E18 RCI_CSN7_S E19 VSSIO E20 DEBUG_TCK E21 FSPI_CLK E22 FSPI_CSN F1 GPIO_6 F2 GPIO_7 F3 GPIO_8 F4 VSSIO F5 VSSIO F6 VSSIO F7 DNC F8 VSS F9 DNC F10 VSS F11 PCIE_VPTX F12 VSS F13 PCIE_VP F14 PLL_DVDD F15 PLL_DVSS F16 PLL_DVSS F17 PLL_DVDD F18 RCI_CSN6_S F19 VDDIO F20 VSSIO F21 FSPI_D0 F22 FSPI_D1_DO G1 GPIO_9 G2 GPIO_10 G3 VSSIO G4 VSSIO G5 VSSIO G6 TSENSE_AVDDH G7 TSENSE_AVSS G8 VDD G9 VSS G10 VDD G11 VSS G12 VDD G13 VSS G14 VDDIO G15 VSSIO G16 VDD G17 VSSIO G18 RCI_CSN5_S G19 RCI_CSN4_S G20 DEBUG_TDO G21 FSPI_D2_WPN G22 FSPI_D3_HN H1 GPIO_11 H2 GPIO_12 H3 VDDIO H4 VSSIO H5 VSSIO H6 VSSIO H7 VDD H8 VSS H9 VDD H10 VSS H11 VDD H12 VSS H13 VDD H14 VSS H15 VDD H16 VSS H17 VDDIO H18 RCI_CSN3_S H19 VSSIO H20 DEBUG_TDI H21 UART_RTS H22 UART_RX J1 GPIO_13 J2 GPIO_14 J3 GPIO_15 J4 DNC J5 DNC J6 VDDIO J7 VSS J8 VDD J9 VSS J10 VDD J11 VSS J12 VDD J13 VSS J14 VDD J15 VSS J16 VDD J17 VSS J18 RCI_CSN2_S J19 RCI_MISO7_S J20 DEBUG_TMS J21 UART_CTS J22 UART_TX K1 VSSIO K2 VSSIO K3 VSSIO K4 DNC K5 DNC K6 VSS K7 VDD K8 VSS K9 VDD K10 VSS K11 VDD K12 VSS K13 VDD K14 VSS K15 VDD K16 VSS K17 VDD K18 VSSIO K19 VSSIO K20 DEBUG_TRSTN K21 RCI_GPIO1 K22 RCI_GPIO0 L1 VSSIO L2 VSSIO L3 VSSIO L4 DNC L5 DNC L6 VDDIO L7 VSS L8 VDD L9 VSS L10 VDD L11 VSS L12 VDD L13 VSS L14 VDD L15 VSS L16 VDD L17 VSS L18 VDDIO L19 RCI_GPIO5 L20 RCI_GPIO4 L21 RCI_GPIO3 L22 RCI_GPIO2 M1 DNC M2 DNC M3 LVDS_VDDIO M4 VSSIO M5 DNC M6 VSS M7 VDD M8 VSS M9 VDD M10 VSS M11 VDD M12 VSS M13 VDD M14 VSS M15 VDD M16 VSS M17 VDD M18 VSS M19 LVDS_VDDIO M20 VSSIO M21 RCI_CSN0_P M22 RCI_CSN0_N N1 DNC N2 DNC N3 VSSIO N4 VSSIO N5 VSSIO N6 VDDIO N7 VSS N8 VDD N9 VSS N10 VDD N11 VSS N12 VDD N13 VSS N14 VDD N15 VSS N16 VDD N17 VSS N18 RCI_GPIO8 N19 RCI_GPIO7 N20 RCI_GPIO6 N21 RCI_SCLK_P N22 RCI_SCLK_N P1 DNC P2 DNC P3 VSSIO P4 LVDS_VDDIO P5 VSSIO P6 VSSIO P7 VDD P8 VSS P9 VDD P10 VSS P11 VDD P12 VSS P13 VDD P14 VSS P15 VDD P16 VSS P17 VDD P18 RCI_GPIO9 P19 LVDS_VDDIO P20 VSSIO P21 RCI_MOSI0_P P22 RCI_MOSI0_N R1 DNC R2 DNC R3 RCI_REF R4 DNC R5 DNC R6 VDD R7 VSS R8 VDD R9 VSS R10 VDD R11 VSS R12 VDD R13 VSS R14 VDD R15 VSS R16 VDD R17 VSS R18 RCI_CSN0_S R19 RCI_SCLK_S R20 RCI_REF R21 RCI_MOSI1_P R22 RCI_MOSI1_N T1 DNC T2 DNC T3 DNC T4 DNC T5 RCI_VDDIO T6 MSFE_AVSS T7 MSFE_PLL_AVDD T8 MSFE_AVSS T9 MSFE_OSC_AVDDH T10 MSFE_AVSS T11 MSFE_AVDD T12 MSFE_AVDD T13 MSFE_AVSS T14 MSFE_OSC_AVDDH T15 MSFE_AVSS T16 MSFE_PLL_AVDD T17 MSFE_AVSS T18 VSSIO T19 RCI_MISO1_S T20 RCI_MISO0_S T21 RCI_MOSI2_P T22 RCI_MOSI2_N U1 DNC U2 DNC U3 DNC U4 DNC U5 VSSIO U6 MSFE_AVDDH U7 MSFE_AVSS U8 MSFE_PLL_AVDDH U9 MSFE_AVSS U10 MSFE_AVDD U11 MSFE_AVSS U12 MSFE_AVSS U13 MSFE_AVDD U14 MSFE_AVSS U15 MSFE_PLL_AVDDH U16 MSFE_AVSS U17 MSFE_AVDDH U18 RCI_VDDIO U19 RCI_MOSI1_S U20 RCI_MOSI0_S U21 RCI_MOSI3_P U22 RCI_MOSI3_N V1 DNC V2 DNC V3 DNC V4 DNC V5 DNC V6 MSFE_AVSS V7 MSFE_AVDDH V8 MSFE_AVSS V9 MSFE_AVDD V10 MSFE_AVSS V11 MSFE_AVSS V12 MSFE_AVSS V13 MSFE_AVSS V14 MSFE_AVDD V15 MSFE_AVSS V16 MSFE_AVDDH V17 MSFE_AVSS V18 RCI_CSN1_S V19 RCI_MOSI3_S V20 RCI_MOSI2_S V21 RCI_CSN1_P V22 RCI_CSN1_N W1 VSSIO W2 LVDS_VDDIO W3 VSSIO W4 VDDIO W5 MSFE_AVSS W6 MSFE_AVDDH W7 MSFE_AVSS W8 MSFE_AVDDH W9 MSFE_AVSS W10 MSFE_AVSS W11 MSFE_AVSS W12 MSFE_AVSS W13 MSFE_AVSS W14 MSFE_AVSS W15 MSFE_AVDDH W16 MSFE_AVSS W17 MSFE_AVDDH W18 MSFE_AVSS W19 VDDIO W20 VSSIO W21 LVDS_VDDIO W22 VSSIO Y1 MSFE_AVSS Y2 MSFE_AVSS Y3 DNC Y4 DNC Y5 DNC Y6 DNC Y7 DNC Y8 MSFE_AVSS Y9 MSFE_AVSS Y10 MSFE_AVSS Y11 MSFE_AVSS Y12 MSFE_AVSS Y13 MSFE_AVSS Y14 MSFE_AVSS Y15 MSFE_AVSS Y16 RCI_MISO2_S Y17 RCI_MISO3_S Y18 RCI_MISO4_S Y19 RCI_MISO5_S Y20 RCI_MISO6_S Y21 MSFE_AVSS Y22 MSFE_ADC_IN AA1 MSFE_AVSS AA2 DNC AA3 MSFE_AVSS AA4 DNC AA5 MSFE_AVSS AA6 MSFE_AVSS AA7 DNC AA8 DNC AA9 MSFE_AVSS AA10 MSFE_AVSS AA11 MSFE_AVSS AA12 MSFE_AVSS AA13 MSFE_AVSS AA14 MSFE_AVSS AA15 DNC AA16 DNC AA17 MSFE_AVSS AA18 MSFE_AVSS AA19 MSFE_CLKOUT AA20 MSFE_AVSS AA21 MSFE_ADC_VCM AA22 MSFE_ADC_IP AB1 MSFE_AVSS AB2 MSFE_AVSS AB3 MSFE_AVSS AB4 MSFE_AVSS AB5 MSFE_AVSS AB6 DNC AB7 MSFE_AVSS AB8 DNC AB9 DNC AB10 DNC AB11 DNC AB12 MSFE_DAC_IP AB13 MSFE_DAC_IN AB14 MSFE_DAC_QP AB15 MSFE_DAC_QN AB16 MSFE_XI AB17 MSFE_XO AB18 MSFE_REFCLKP AB19 MSFE_REFCLKN AB20 MSFE_ADC_QP AB21 MSFE_ADC_QN AB22 MSFE_AVSS