Tsi572 Pinlist -- Integrated Device Technology Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as "reserved" or "undefined" are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk. Revision History September 11, 2013 To enable ports 2 and 4 to be configured through hardware as well as software, the following updates were completed: * Changed the name of the V1 pin to SP4_MODESEL from NC * Changed the name of the Y13 pin to SP2_MODESEL from NC December 9, 2009 * This document was updated for IDT formatting. No technical changes were made. July 15, 2008 * The N4 signal was changed from TRI_b to VDD_IO. Pin Signal ---------------------- A1 NO_BALL A2 VSS A3 VSS A4 VSS A5 VSS A6 VSS A7 VSS A8 SP6_TD_P A9 VSS A10 SP6_TC_N A11 VSS A12 SP6_TB_P A13 VSS A14 SP6_TA_N A15 VSS A16 VSS A17 VSS A18 VSS A19 VSS A20 VSS B1 VSS B2 VSS B3 VSS B4 VSS B5 VSS B6 VSS B7 VSS B8 SP6_TD_N B9 VSS B10 SP6_TC_P B11 SP_VDD B12 SP6_TB_N B13 VSS B14 SP6_TA_P B15 SP_VDD B16 VSS B17 VSS B18 S_CLK_P B19 S_CLK_N B20 VSS C1 VSS C2 VSS C3 VSS C4 VSS C5 VSS C6 VSS C7 VSS C8 SP_VDD C9 VSS C10 SP_VDD C11 VSS C12 SP_VDD C13 VSS C14 SP_VDD C15 VSS C16 VSS C17 VSS C18 REF_AVDD C19 VSS C20 REF_AVDD D1 VSS D2 SP_VDD D3 VSS D4 VSS D5 VSS D6 VSS D7 VSS D8 SP6_RD_N D9 VSS D10 SP6_RC_P D11 SP6_REXT D12 SP6_RB_N D13 VSS D14 SP6_RA_P D15 VSS D16 VSS D17 VSS D18 VSS D19 VSS D20 VSS E1 SP0_TA_N E2 SP0_TA_P E3 SP_VDD E4 SP0_RA_P E5 SP0_RA_N E6 VSS E7 VSS E8 SP6_RD_P E9 SP_AVDD E10 SP6_RC_N E11 SP_AVDD E12 SP6_RB_P E13 SP_VDD E14 SP6_RA_N E15 VSS E16 VSS E17 VSS E18 VSS E19 VSS E20 VSS F1 VSS F2 VSS F3 VSS F4 VSS F5 SP_VDD F6 VSS F7 VSS F8 VSS F9 VSS F10 VSS F11 SP_AVDD F12 VSS F13 VSS F14 VSS F15 VSS F16 SP_AVDD F17 NC F18 VSS F19 VSS F20 VSS G1 SP0_TB_P G2 SP0_TB_N G3 SP_VDD G4 SP0_RB_N G5 SP0_RB_P G6 VSS G7 VSS G8 VDD G9 VSS G10 VDD G11 VSS G12 VDD G13 VSS G14 VDD G15 VSS G16 NC G17 NC G18 SP_VDD G19 NC G20 NC H1 VSS H2 SP_VDD H3 VSS H4 SP0_REXT H5 SP_AVDD H6 VSS H7 VDD H8 VSS H9 VDD H10 VSS H11 VDD H12 VSS H13 VDD H14 VSS H15 SP_AVDD H16 SP_VDD H17 VSS H18 VSS H19 VSS H20 VSS J1 SP0_TC_N J2 SP0_TC_P J3 SP_VDD J4 SP0_RC_P J5 SP0_RC_N J6 VSS J7 VSS J8 VDD J9 VSS J10 VDD J11 VSS J12 VDD J13 VSS J14 VDD J15 VSS J16 NC J17 NC J18 SP_VDD J19 NC J20 NC K1 VSS K2 VSS K3 VSS K4 VSS K5 SP_AVDD K6 VSS K7 VDD K8 VSS K9 VDD K10 VSS K11 VDD K12 VSS K13 VDD K14 VSS K15 VSS K16 SP_AVDD K17 SP4_REXT K18 VSS K19 SP_VDD K20 VSS L1 SP0_TD_P L2 SP0_TD_N L3 SP_VDD L4 SP0_RD_N L5 SP0_RD_P L6 SP_AVDD L7 VSS L8 VDD L9 VSS L10 VDD L11 VSS L12 VDD L13 VSS L14 VDD L15 SP_AVDD L16 SP4_RB_P L17 SP4_RB_N L18 SP_VDD L19 SP4_TB_N L20 SP4_TB_P M1 VSS M2 SP_VDD M3 VSS M4 VSS M5 VSS M6 VSS M7 VDD M8 VSS M9 VDD M10 VSS M11 VDD M12 VSS M13 VDD M14 VSS M15 VSS M16 SP_VDD M17 VSS M18 VSS M19 VSS M20 VSS N1 VSS N2 SP4_PWRDN N3 SP5_PWRDN N4 VDD_IO N5 VSS N6 VSS N7 VSS N8 VDD N9 VSS N10 VDD N11 VSS N12 VDD N13 VSS N14 VDD N15 VSS N16 SP4_RA_N N17 SP4_RA_P N18 SP_VDD N19 SP4_TA_P N20 SP4_TA_N P1 SP6_PWRDN P2 VDD_IO P3 SP7_PWRDN P4 VSS P5 VSS P6 VSS P7 VDD P8 VSS P9 VDD P10 VSS P11 VDD P12 VSS P13 VDD P14 VSS P15 VSS P16 VSS P17 VSS P18 VSS P19 SP_VDD P20 VSS R1 VSS R2 NC R3 NC R4 VDD_IO R5 VSS R6 VSS R7 VSS R8 VSS R9 VSS R10 VSS R11 SP_AVDD R12 VSS R13 SP_AVDD R14 VSS R15 VSS R16 I2C_SA[0] R17 I2C_SA[1] R18 VSS R19 MCES R20 BCE T1 VSS T2 VDD_IO T3 VDD_IO T4 VSS T5 VSS T6 VSS T7 SP2_RA_N T8 SP_VDD T9 SP2_RB_P T10 SP_AVDD T11 NC T12 SP_VDD T13 NC T14 SP_AVDD T15 VSS T16 SP_IO_SPEED[0] T17 I2C_SEL T18 VSS T19 SP_RX_SWAP T20 SP_TX_SWAP U1 VSS U2 INT_B U3 VSS U4 VDD_IO U5 SP6_MODESEL U6 VSS U7 SP2_RA_P U8 VSS U9 SP2_RB_N U10 SP2_REXT U11 NC U12 VSS U13 NC U14 NC U15 VSS U16 SP_IO_SPEED[1] U17 VDD_IO U18 I2C_DISABLE U19 VDD_IO U20 TMS V1 SP4_MODESEL V2 VDD_IO V3 SW_RST_B V4 NC V5 NC V6 VSS V7 SP_VDD V8 VSS V9 SP_VDD V10 VSS V11 SP_VDD V12 VSS V13 SP_VDD V14 VSS V15 VSS V16 SP0_MODESEL V17 VSS V18 VSS V19 TDO V20 TDI W1 VSS W2 NC W3 VSS W4 VDD_IO W5 NC W6 VSS W7 SP2_TA_P W8 VSS W9 SP2_TB_N W10 SP_VDD W11 NC W12 VSS W13 NC W14 SP_VDD W15 VSS W16 I2C_MA W17 SP2_PWRDN W18 I2C_SD W19 VDD_IO W20 TRST_B Y1 P_CLK Y2 VDD_IO Y3 HARD_RST_B Y4 VSS Y5 VSS Y6 VSS Y7 SP2_TA_N Y8 VSS Y9 SP2_TB_P Y10 VSS Y11 NC Y12 VSS Y13 SP2_MODESEL Y14 VSS Y15 VSS Y16 SP1_PWRDN Y17 SP3_PWRDN Y18 VSS Y19 I2C_SCLK Y20 TCK