Tsi578 Pinlist (Document number 80B803A_PN002_05) ---------------------------------------------------------------------- This document lists the pinout for the Tsi578 (Part number TSI578-10Gxxx). For more information about the Tsi578 pinlist or its signal descriptions, see the Tsi578 User Manual. Note, this document was updated for IDT formatting. There have been no technical changes. Copyright © 2009 Integrated Device Technology, Inc.All Rights Reserved. GENERAL DISCLAIMER Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as "reserved" or "undefined" are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk. The IDT logo is registered to Integrated Device Technology, Inc. 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A2 VSS A3 VSS A4 VSS A5 VSS A6 VSS A7 SP14_TD_P A8 VSS A9 SP14_TC_N A10 VSS A11 SP14_TB_P A12 VSS A13 SP14_TA_N A14 VSS A15 SP6_TD_P A16 VSS A17 SP6_TC_N A18 VSS A19 SP6_TB_P A20 VSS A21 SP6_TA_N A22 VSS A23 VSS A24 VSS A25 VSS A26 VSS B1 VSS B2 SP_VDD B3 VSS B4 VSS B5 VSS B6 VSS B7 SP14_TD_N B8 VSS B9 SP14_TC_P B10 SP_VDD B11 SP14_TB_N B12 VSS B13 SP14_TA_P B14 SP_VDD B15 SP6_TD_N B16 VSS B17 SP6_TC_P B18 SP_VDD B19 SP6_TB_N B20 VSS B21 SP6_TA_P B22 SP_VDD B23 VSS B24 S_CLK_P B25 S_CLK_N B26 VSS C1 SP0_TA_N C2 SP0_TA_P C3 SP_VDD C4 SP0_RA_P C5 SP0_RA_N C6 SP_VDD C7 SP_VDD C8 VSS C9 SP_VDD C10 VSS C11 SP_VDD C12 VSS C13 SP_VDD C14 VSS C15 SP_VDD C16 VSS C17 SP_VDD C18 VSS C19 SP_VDD C20 VSS C21 SP_VDD C22 VSS C23 VSS C24 REF_AVDD C25 VSS C26 REF_AVDD D1 VSS D2 VSS D3 VSS D4 VSS D5 SP_VDD D6 VSS D7 SP14_RD_N D8 VSS D9 SP14_RC_P D10 SP14_REXT D11 SP14_RB_N D12 VSS D13 SP14_RA_P D14 VSS D15 SP6_RD_N D16 VSS D17 SP6_RC_P D18 SP6_REXT D19 SP6_RB_N D20 VSS D21 SP6_RA_P D22 VSS D23 VSS D24 VSS D25 VSS D26 VSS E1 SP0_TB_P E2 SP0_TB_N E3 SP_VDD E4 SP0_RB_N E5 SP0_RB_P E6 SP_VDD E7 SP14_RD_P E8 SP14_AVDD E9 SP14_RC_N E10 SP14_AVDD E11 SP14_RB_P E12 SP_VDD E13 SP14_RA_N E14 VSS E15 SP6_RD_P E16 SP6_AVDD E17 SP6_RC_N E18 SP6_AVDD E19 SP6_RB_P E20 SP_VDD E21 SP6_RA_N E22 VSS E23 VSS E24 VSS E25 VSS E26 VSS F1 VSS F2 SP_VDD F3 VSS F4 SP0_REXT F5 SP0_AVDD F6 VSS F7 SP_VDD F8 VSS F9 SP_VDD F10 VSS F11 SP_VDD F12 VSS F13 SP_VDD F14 VSS F15 SP_VDD F16 VSS F17 SP_VDD F18 VSS F19 SP_VDD F20 VSS F21 SP_VDD F22 VSS F23 VSS F24 VSS F25 VSS F26 VSS G1 SP0_TC_N G2 SP0_TC_P G3 SP_VDD G4 SP0_RC_P G5 SP0_RC_N G6 SP_VDD G7 VSS G8 SP_VDD G9 VSS G10 SP_VDD G11 VSS G12 SP_VDD G13 VSS G14 SP_VDD G15 VSS G16 SP_VDD G17 VSS G18 SP_VDD G19 VSS G20 SP_VDD G21 SP_VDD G22 SP12_RD_P G23 SP12_RD_N G24 SP_VDD G25 SP12_TD_N G26 SP12_TD_P H1 VSS H2 VSS H3 VSS H4 VSS H5 SP0_AVDD H6 VSS H7 SP_VDD H8 VSS H9 VSS H10 VSS H11 VSS H12 VSS H13 VSS H14 VSS H15 VSS H16 VSS H17 VSS H18 VSS H19 VSS H20 SP_VDD H21 VSS H22 SP12_AVDD H23 VSS H24 VSS H25 VSS H26 VSS J1 SP0_TD_P J2 SP0_TD_N J3 SP_VDD J4 SP0_RD_N J5 SP0_RD_P J6 SP_VDD J7 VSS J8 VSS J9 VSS J10 VDD J11 VSS J12 VDD J13 VSS J14 VDD J15 VSS J16 VDD J17 VSS J18 VDD J19 VSS J20 VSS J21 SP_VDD J22 SP12_RC_N J23 SP12_RC_P J24 SP_VDD J25 SP12_TC_P J26 SP12_TC_N K1 VSS K2 SP_VDD K3 VSS K4 VSS K5 VSS K6 VSS K7 SP_VDD K8 VSS K9 VDD K10 VSS K11 VDD K12 VSS K13 VDD K14 VSS K15 VDD K16 VSS K17 VDD K18 VSS K19 VSS K20 SP_VDD K21 VSS K22 SP12_AVDD K23 SP12_REXT K24 VSS K25 SP_VDD K26 VSS L1 SP8_TA_N L2 SP8_TA_P L3 SP_VDD L4 SP8_RA_P L5 SP8_RA_N L6 SP_VDD L7 VSS L8 VSS L9 VSS L10 VDD L11 VSS L12 VDD L13 VSS L14 VDD L15 VSS L16 VDD L17 VSS L18 VDD L19 VSS L20 VSS L21 SP_VDD L22 SP12_RB_P L23 SP12_RB_N L24 SP_VDD L25 SP12_TB_N L26 SP12_TB_P M1 VSS M2 VSS M3 VSS M4 VSS M5 SP_VDD M6 VSS M7 SP_VDD M8 VSS M9 VDD M10 VSS M11 VDD M12 VSS M13 VDD M14 VSS M15 VDD M16 VSS M17 VDD M18 VSS M19 VSS M20 SP_VDD M21 VSS M22 SP_VDD M23 VSS M24 VSS M25 VSS M26 VSS N1 SP8_TB_P N2 SP8_TB_N N3 SP_VDD N4 SP8_RB_N N5 SP8_RB_P N6 SP_VDD N7 VSS N8 VSS N9 VSS N10 VDD N11 VSS N12 VDD N13 VSS N14 VDD N15 VSS N16 VDD N17 VSS N18 VDD N19 VSS N20 VSS N21 SP_VDD N22 SP12_RA_N N23 SP12_RA_P N24 SP_VDD N25 SP12_TA_P N26 SP12_TA_N P1 VSS P2 SP_VDD P3 VSS P4 SP8_REXT P5 SP8_AVDD P6 VSS P7 SP_VDD P8 VSS P9 VDD P10 VSS P11 VDD P12 VSS P13 VDD P14 VSS P15 VDD P16 VSS P17 VDD P18 VSS P19 VSS P20 SP_VDD P21 VSS P22 VSS P23 VSS P24 VSS P25 SP_VDD P26 VSS R1 SP8_TC_N R2 SP8_TC_P R3 SP_VDD R4 SP8_RC_P R5 SP8_RC_N R6 SP_VDD R7 VSS R8 VSS R9 VSS R10 VDD R11 VSS R12 VDD R13 VSS R14 VDD R15 VSS R16 VDD R17 VSS R18 VDD R19 VSS R20 VSS R21 SP_VDD R22 SP4_RD_P R23 SP4_RD_N R24 SP_VDD R25 SP4_TD_N R26 SP4_TD_P T1 VSS T2 VSS T3 VSS T4 VSS T5 SP8_AVDD T6 VSS T7 SP_VDD T8 VSS T9 VDD T10 VSS T11 VDD T12 VSS T13 VDD T14 VSS T15 VDD T16 VSS T17 VDD T18 VSS T19 I2C_SA[0] T20 SP_VDD T21 VSS T22 SP4_AVDD T23 VSS T24 VSS T25 VSS T26 VSS U1 SP8_TD_P U2 SP8_TD_N U3 SP_VDD U4 SP8_RD_N U5 SP8_RD_P U6 SP_VDD U7 VSS U8 VSS U9 VSS U10 VDD U11 VSS U12 VDD U13 VSS U14 VDD U15 VSS U16 VDD U17 VSS U18 VDD U19 I2C_SA[1] U20 VSS U21 SP_VDD U22 SP4_RC_N U23 SP4_RC_P U24 SP_VDD U25 SP4_TC_P U26 SP4_TC_N V1 VSS V2 VDD_IO V3 VSS_IO V4 VSS V5 VSS_IO V6 VDD_IO V7 SP_VDD V8 VSS V9 VDD V10 VSS V11 VDD V12 VSS V13 VDD V14 VSS V15 VDD V16 VSS V17 VDD V18 VSS V19 BCE V20 SP_VDD V21 VSS V22 SP4_AVDD V23 SP4_REXT V24 VSS V25 SP_VDD V26 VSS W1 VSS_IO W2 SP4_PWRDN W3 SP5_PWRDN W4 VDD_IO W5 SP6_PWRDN W6 SP7_PWRDN W7 SP14_PWRDN W8 VSS_IO W9 VSS W10 VSS W11 VSS W12 VSS W13 VSS W14 VSS W15 VSS W16 VSS W17 VSS W18 VSS W19 VSS_IO W20 I2C_SEL W21 SP_VDD W22 SP4_RB_P W23 SP4_RB_N W24 SP_VDD W25 SP4_TB_N W26 SP4_TB_P Y1 SP8_PWRDN Y2 VDD_IO Y3 SP9_PWRDN Y4 SP10_PWRDN Y5 VSS_IO Y6 SP11_PWRDN Y7 VDD_IO Y8 SP15_PWRDN Y9 SP_VDD Y10 VSS Y11 SP_VDD Y12 VSS Y13 SP_VDD Y14 VSS Y15 SP_VDD Y16 VSS Y17 SP_VDD Y18 VSS_IO Y19 SP_RX_SWAP Y20 SP_TX_SWAP Y21 VSS Y22 SP_VDD Y23 VSS Y24 VSS Y25 VSS Y26 VSS AA1 VSS_IO AA2 SP12_PWRDN AA3 SP13_PWRDN AA4 VDD_IO AA5 VSS AA6 SP_VDD AA7 VSS AA8 SP_VDD AA9 VSS AA10 SP_VDD AA11 VSS AA12 SP_VDD AA13 VSS AA14 SP_VDD AA15 VSS AA16 SP_VDD AA17 VSS AA18 SP_VDD AA19 VSS AA20 SP_VDD AA21 SP_VDD AA22 SP4_RA_N AA23 SP4_RA_P AA24 SP_VDD AA25 SP4_TA_P AA26 SP4_TA_N AB1 SP4_MODESEL AB2 VDD_IO AB3 SP6_MODESEL AB4 SP8_MODESEL AB5 VSS_IO AB6 SP2_RA_N AB7 SP_VDD AB8 SP2_RB_P AB9 SP2_AVDD AB10 SP2_RC_N AB11 SP2_AVDD AB12 SP2_RD_P AB13 VSS AB14 SP10_RA_N AB15 SP_VDD AB16 SP10_RB_P AB17 SP10_AVDD AB18 SP10_RC_N AB19 SP10_AVDD AB20 SP10_RD_P AB21 VSS AB22 VSS AB23 VSS AB24 VSS AB25 SP_VDD AB26 VSS AC1 VSS_IO AC2 INT_B AC3 SP10_MODESEL AC4 VDD_IO AC5 VSS AC6 SP2_RA_P AC7 VSS AC8 SP2_RB_N AC9 SP2_REXT AC10 SP2_RC_P AC11 VSS AC12 SP2_RD_N AC13 VSS AC14 SP10_RA_P AC15 VSS AC16 SP10_RB_N AC17 SP10_REXT AC18 SP10_RC_P AC19 VSS AC20 SP10_RD_N AC21 VSS AC22 SP_IO_SPEED[0] AC23 SP_IO_SPEED[1] AC24 I2C_DISABLE AC25 VDD_IO AC26 TMS AD1 N/C AD2 VDD_IO AD3 SW_RST_B AD4 N/C AD5 VSS_IO AD6 SP_VDD AD7 VSS AD8 SP_VDD AD9 VSS AD10 SP_VDD AD11 VSS AD12 SP_VDD AD13 VSS AD14 SP_VDD AD15 VSS AD16 SP_VDD AD17 VSS AD18 SP_VDD AD19 VSS AD20 SP_VDD AD21 VSS_IO AD22 SP0_MODESEL AD23 SP2_MODESEL AD24 MCES AD25 TDO AD26 TDI AE1 VSS_IO AE2 N/C AE3 VSS AE4 VDD_IO AE5 SP_VDD AE6 SP2_TA_P AE7 VSS AE8 SP2_TB_N AE9 SP_VDD AE10 SP2_TC_P AE11 VSS AE12 SP2_TD_N AE13 SP_VDD AE14 SP10_TA_P AE15 VSS AE16 SP10_TB_N AE17 SP_VDD AE18 SP10_TC_P AE19 VSS AE20 SP10_TD_N AE21 VSS AE22 I2C_MA AE23 SP2_PWRDN AE24 I2C_SD AE25 VDD_IO AE26 TRST_B AF1 P_CLK AF2 HARD_RST_B AF3 SP12_MODESEL AF4 SP14_MODESEL AF5 VSS AF6 SP2_TA_N AF7 VSS AF8 SP2_TB_P AF9 VSS AF10 SP2_TC_N AF11 VSS AF12 SP2_TD_P AF13 VSS AF14 SP10_TA_N AF15 VSS AF16 SP10_TB_P AF17 VSS AF18 SP10_TC_N AF19 VSS AF20 SP10_TD_P AF21 VSS_IO AF22 SP1_PWRDN AF23 SP3_PWRDN AF24 VSS_IO AF25 I2C_SCLK AF26 TCK