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Staff Digital Verification Engineer

Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor company based in Bengaluru, India, specializing in high-performance chip design for global 5G/6G, defence, satellite communication, and industrial IoT markets. Backed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

Job Description

Preferred

  • Experience with Cadence verification flow and tools like Vmanager, Xcelium, and Simvision is a great plus.
  • Experience in Analog-mixed signal (AMS) in the Cadence Virtuoso suite is desired.
  • Responsibilities 

    • Working closely with the Digital and RF/Analog design leads to understanding the digital design functionality.
    • Propose and develop a detailed test plan based on specification and use cases.
    • Follow the shift-left approach and develop test cases alongside the design activities.
    • Set SV-UVM verification flow from scratch, including developing RAL, UVCs, top-level testbench, simulation setup, and unit test cases.
    • Create test cases in a methodical fashion with UVM and keep track of the coverage.
    • Work with the PD engineer to run gate-level simulations.
    • Properly document the test cases and regression results and submit them on schedule.
    • Support the design team with bring-up and debugging in the lab.

    Requirements

    • B.E./B.Tech. with 7+ years or M.S./M.Tech. with 5+ years in digital design and verification.
    • Proven experience leading SV-UVM-based verification from spec/use-case development to testbench and test case creation.
    • Hands-on in building SV-UVM environments, RAL models, UVCs, and debugging test cases.
    • Strong grasp of modern digital verification methodologies and techniques (UVM, OVM).
    • Skilled in test planning, coverage modeling (functional/code), and regression setup.
    • Experience with RTL and gate-level simulations and debugging.
    • Excellent communication, presentation, and documentation skills.
    • Job Title

      Staff Digital Verification Engineer

    • Department

      Engineering

    • Location

      India – Bangalore Design Center