Axiro Semiconductor Pvt. Ltd. is a leading fabless semiconductor company based in Bengaluru, India, specializing in high-performance chip design for global 5G/6G, defence, satellite communication, and industrial IoT markets. Backed by the Murugappa Group through CG Power, Axiro leverages advanced design capabilities and strategic global manufacturing partnerships to deliver millions of ICs. With a strong focus on innovation, IP ownership in India, and sustainable growth, Axiro is at the forefront of India’s semiconductor mission.

Job Description

Preferred:

• Experience in power amplifier design.
• Familiarity with EM simulation tools: EMX, Keysight Momentum, HFSS.
• Exposure to SOI and GaAs technologies.
• Background in analog/mixed-signal design (e.g., BGR, op-amps) and Verilog-based RTL.
• Understanding of post-silicon qualification (e.g., ESD, HTOL).
• Work with the validation engineers to bring up the chip in the lab and optimize the setting tomeet the design specification.

Responsibilities 

Work independently to develop innovative and differentiating RFIC blocks and topologies for high-performance ICs.

• Working closely with the chip-lead to derive specifications for RF sub-blocks.
• Do literature survey and propose new innovative architectures to meet the design specifications.
• Work diligently to optimize the design to get the best out of the technology.
• Build simulation test benches and run extensive simulations using Cadence Virtuoso/ADS suite.
• Do RFIC layout and run EM extraction to capture parasitic LRC accurately.
• Document the design procedure and progress in a periodic manner.
• Collaborate and guide other designers and review their work.

Requirements

M.Tech. graduate with hands-on experience in RFIC design or 2+years with hands on experience.

• Experience designing RF blocks: LNA, Mixer, Switch, PA, VGA, etc.
• Strong foundation in amplifiers, matching networks, current mirrors, and key RF metrics (Gain,
• NF, IIP3, OP1dB, ACPR, EVM).
• Solid understanding of DC biasing, frequency response, stability, noise, and nonlinearity (IIP3, IP1dB).
• Exposure to tapeout, lab bring-up, and characterization.
• Proficient in Keysight ADS and Cadence Virtuoso (Schematic, Maestro, ADEXL, Layout XL, Spectre/AMS).
• Strong communication skills and a collaborative mindset for SoC development.